Secure Computation Laboratory

Syed Kamran Haider

PhD Student
Electrical & Computer Engineering
University of Connecticut
Office: ITE 423, 371 Fairfield Way, Storrs CT 06269
Email: syed.haider@uconn.edu
Web: Personal Page

Biography

I am currently pursuing a Ph.D. in Computer Engineering supervised by Marten van Dijk at University of Connecticut. My research interests include Computer Architecture and Hardware Security. I work on hardware and hardware-software co-design mechanisms for scalability and security of concurrent algorithms running on multi-core platforms. Before coming to UConn, I did my Masters in Embedded Computing Systems as a joint degree from NTNU Trondheim, Norway and TU Kaiserslautern, Germany. I did my Bachelors in Electronics Engineering from National University of Science & Technology, Islamabad, Pakistan.

Research Interests

• Computer Architecture
• Hardware Security
• Multicore Architecture & Modeling
• Cache Coherence Protocols
• Parallel Programming
• Performance Analysis

Research Projects

• Secure Processor Architectures
  Oblivious RAM (ORAM) is a well known primitive that obfuscates the access patterns from a secure processor to an untrusted memory. However, the performance overhead incurred by ORAM is still considered a major challenge that makes it infeasible for practical systems. In order to mitigate this challenge, previously we have designed, in collaboration with MIT, a dynamic prefetcher for ORAM making it more efficient for secure general purpose computing. To completely eliminate the performance overheads, currently we are exploring new ORAM constructions that are inherently efficient for current and future computing demands.
  Orthogonally, we have explored and demonstrated how capability systems (for program control flow verification) and memory integrity verification schemes can be efficiently implemented together in processor architectures to verify correct execution of the programs even in the presence of adversarial behavior.


• Efficient Shared-Memory Multicore Architectures
  High memory contention is generally agreed to be a worst-case scenario for concurrent data structures. However, there are currently few architectural mechanisms to allow scaling contended data structures at high thread counts. In this project, we investigate hardware support for scalable contended data structures. We have proposed Lease/Release, a simple addition to standard directory-based cache coherence protocols, allowing participants to lease memory, at the granularity of cache lines, for a short, bounded period of time. Our analysis shows that Lease/Release can significantly reduce the overheads of contention for both non-blocking (lock-free) and lock-based data structure implementations, while ensuring that no deadlocks are introduced. Currently we are exploring new hardware-software co-deign mechanisms for efficient transactional memory support on top of modern cache coherence protocols under high contention.


• HaTCh: A Formal Framework of Hardware Trojan Design and Detection
  State of the art research has shown that existing Hardware Trojans (HT) detection techniques, which claim to detect all publicly available HT benchmarks, can still be defeated by carefully designing new sophisticated HTs. The reason being that these techniques consider the HT landscape to be limited only to the publicly known HT benchmarks. In this work, we introduce a formal classification of trigger activated HTs which represents a vast landscape of possible HT designs beyond the publicly known state of the art HTs. We then present HaTCh, a pre-silicon logic testing based powerful detection algorithm which detects any HT from the above mentioned class of deterministic HTs with overwhelming probability 1-negl(λ). Given certain global characteristics regarding the stealthiness of the HT within this class, the computational complexity of our algorithm for practical HTs scales polynomially with the number of wires in the IP core. We argue that those HTs that fall outside the characterized class use HT design principles that allow HTs which can never be detected within the pre-silicon logic testing based paradigm.

Publications

• Syed Kamran Haider, William Hasenplaugh, and Dan Alistarh, "Lease/Release: Architectural Support for Scaling Contended Data Structures", Principles and Practice of Parallel Programming (PPoPP 2016) [Paper]
• Stefan Scholl, Syed Kamran Haider, and Norbet Wehn, "An Efficient Soft Decision Reed-Solomon Decoder for Moderate Throughput", 18th IEEE Mediterranean Electrotechnical Conference (MELECON 2016)
• Syed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, and Marten van Dijk, "M-MAP: Multi-Factor Memory Authentication for Secure Embedded Processors", IEEE International Conference on Computer Design (ICCD 2015)
• Xiangyao Yu, Syed Kamran Haider, Ling Ren, Christopher Fletcher, Albert Kwon, Marten van Dijk, Srinivas Devadas, "PrORAM: Dynamic Prefetcher for Oblivious RAM", International Symposium on Computer Architecture (ISCA 2015) [Paper]
• Masab Ahmad, Syed Kamran Haider, Farrukh Hijaz, Marten van Dijk, Omer Khan, "Exploring the Performance Implications of Memory Safety Primitives in Many-core Processors Executing Multi-threaded Workloads", Hardware and Architectural Support for Security and Privacy (HASP 2015)
• Viktoria Grindle, Syed Kamran Haider, John Magee, Marten van Dijk, "Virtual Fingerprint: Image-Based Authentication Increases Privacy for Users of Mouse-Replacement Interfaces", International Conference on Human-Computer Interaction (HCII 2015)
• Syed Kamran Haider, Devu Manikantan Shila, Marten van Dijk, "Security Agents for Embedded Intrusion Detection", Circuit Cellar Magazine, April 2015, Issue 297. circuitcellar.com/magazine
• Syed Kamran Haider, Chenglu Jin, Masab Ahmad, Devu Manikantan Shila, Omer Khan, Marten van Dijk, "HaTCh: A Formal Framework of Hardware Trojans Design and Detection", Cryptology ePrint Archive, Report 2014/943, 2014. [Paper]