Secure Computation Laboratory

Secure Multicore Architecture Design

The emergence of general-purpose system-on-chip (SoC) architectures has given rise to a number of significant security challenges. The current trend in SoC design is system-level integration of heterogeneous technologies consisting of a large number of processing elements such as programmable RISC cores, memory, DSPs, and accelerator function units/ASIC. These processing elements may come from different providers, and application executable code may have varying levels of trust. Some of the pressing architecture design questions are: (1) how to implement multi-level user-define security; (2) how to optimally and securely share resources and data among processing elements; (3) how to use reconfiguration for the purpose of obfuscation to attackers.

In this talk, I will present two design cases of secure multicore architecture: (1) Securitas, an architectural framework for integrating multiple processing elements, which may include secure and non-secure cores, into the same chip design, while (i) maintaining individual tenant security, (ii) preventing data leakage and corruption, and (iii) promoting collaboration among the tenants. The Securitas architecture is based on a programmable secure router interface and trust-aware routing algorithm; (2) Sphinx, a hardware-software co-design architecture for binary code and runtime obfuscation. The Sphinx architecture uses binary code diversification and self-reconfigurable processing elements to enable the functionality of an application to remain the same while the binary code and architecture states are obfuscated and operate differently to attackers. This approach dramatically reduces an attacker's ability to exploit information gained from one deployment to attack another deployment.